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Features
* Utilizes the ARM7TDMITM ARM(R) Thumb(R) Processor Core
- High-performance 32-bit RISC Architecture - High-density 16-bit Instruction Set - Leader in MIPS/Watt - Embedded ICE (In-circuit Emulation) 8K Bytes Internal SRAM Fully-programmable External Bus Interface (EBI) - 128 M Bytes of Maximum External Address Space - 8 Chip Selects - Software Programmable 8-/16-bit External Databus 8-level Priority, Individually Maskable, Vectored Interrupt Controller - 8 External Interrupts, Including a High-priority, Low-latency Interrupt Request 58 Programmable I/O Lines 6-channel 16-bit Timer/Counter - Six External Clock Inputs - Two Multi-purpose I/O Pins per Channel Three USARTs Master/Slave SPI Interface - 8-bit to 16-bit Programmable Data Length - Four External Slave Chip Selects Programmable Watchdog Timer 8-channel 10-bit ADC 2-channel 10-bit DAC Clock Generator with On-chip Main Oscillator and PLL for Multiplication - 3 MHz to 20 MHz Frequency Range Main Oscillator Real-time Clock with On-chip 32 kHz Oscillator - Battery Backup Operation and External Alarm 8-channel Peripheral Data Controller for USARTs and SPIs Advanced Power Management Controller (APMC) - Normal, Wait, Slow, Standby and Power-down Modes IEEE 1149.1 JTAG Boundary-scan on All Digital Pins Fully Static Operation: 0 Hz to 33 MHz Internal Frequency Range at VDDCORE = 3.0 V, 85C 2.7V to 3.6V Core Operating Range 2.7V to 5.5V I/O Operating Range 2.7V to 3.6V Analog Operating Range 1.8V to 3.6V Backup Battery Operating Range 2.7V to 3.6V Oscillator and PLL Operating Range -40C to +85C Temperature Range Available in a 176-lead TQFP or 176-ball BGA Package
* *
* * * * * * * * * * * * * * * * * * * * *
AT91 ARM(R) Thumb(R) Microcontroller AT91M55800A Electrical Characteristics
Description
The AT91M55800A is a member of the Atmel AT91 16-/32-bit microcontroller family, which is based on the ARM7TDMI processor core. This processor has a high performance 32-bit RISC architecture with a high-density 16-bit instruction set and very low power consumption. In addition, a large number of internally banked registers result in very fast exception handling, making the device ideal for real-time control applications. The fully-programmable External Bus Interface provides a direct connection to off-chip memory in as fast as one clock cycle for a read or write operation. An eight-level priority vectored interrupt controller in conjunction with the Peripheral Data Controller significantly improve the real-time performance of the device. The device is manufactured using Atmel's high-density CMOS technology. By combining the ARM7TDMI processor core with an on-chip SRAM and a wide range of peripheral functions, analog interfaces and low-power oscillators on a monolithic chip,
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the Atmel AT91M55800A is a powerful microcontroller that provides a highly-flexible and cost-effective solution to many ultra low-power applications.
Absolute Maximum Ratings*
Operating Temperature (Industrial).......-40C to +85C Storage Temperature............................-60C to + 150C Voltage on VDDBU Powered Input Pins with Respect to Ground: ...........................-0.3V to +3.9V Voltage on Any Other Input Pin with Respect to Ground......................... ...-0.3V to +5.5V Maximum Operating Voltage (VDDCORE, VDDA, VDDPLL and VDDBU) ......................... 3.6V Maximum Operating Voltage (VDDIO) ....................... 5.5V DC Output Current (VDDIO)...................................... 4 mA DC Output Current (VDDBU)..................................... 6 mA *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
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DC Characteristics
The following characteristics are applicable to the Operating Temperature range: TA = -40C to 85C, unless otherwise specified and are certified for a Junction Temperature up to TJ = 100C. Table 1. DC Characteristics
Symbol VDDBU VDDCORE VDDPLL VDDA VDDIO Parameter DC Supply Backup Battery DC Supply Core DC Supply Oscillator and PLL DC Supply Analog I/Os DC Supply Digital I/Os NRSTBU and WAKEUP pins VIL Input Low-level Voltage Other pins NRSTBU and WAKEUP pins VIH Input High-level Voltage Other pins SHDN pin: VDDBU = 3.0V IOL = 0.3 mA(2) Other pins: IOL = 4 mA(2) IOL = 0 mA(2) SHDN pin: VDDBU = 3.0V IOH = 0.3 mA(2) Other pins: IOH = 4 mA(2) IOH = 0 mA(2 Input Leakage Current Blocks powered by VDDBU, VDDBU = 3.6V, VIN = 0 IPULL Input Pull-up Current Blocks powered by VDDIO, VDDA and VDDPLL, VDD = 3.6V(1), VIN = 0 176-TQFP Package VDD(1) = VDDCORE = 3.6V, MCK = 0 Hz ISC Static Current All inputs driven TMS, TDI, TCK, NRST = 1 1. VDD is applicable to VDDIO, VDDA and VDDPLL. 2. IO = Output Current. TA = 85C 500 TA = 25C VDDBU - 0.1 V VDD - 0.4(1) VDD - 0.2(1) 392 352 A 280 6 25 A pF nA -0.3 0.7 x VDDBU 2 Conditions Min 1.8 2.7 VDDCORE VDDCORE VDDCORE -0.3 Typ Max 3.6 3.6 3.6 3.6 VDDCORE + 2.0 or 5.5 0.3 x VDDBU 0.8 VDDBU + 0.3 VDD + 0.3(1) GNDBU + 0.1 V 0.4 0.2 V Units V V V V V
V
VOL
Output Low-level Voltage
VOH
Output High-level Voltage
ILEAK
CIN
Input Capacitance
Notes:
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Power Consumption
The values in the following tables are measured values in the operating conditions indicated (i.e., V DDIO = 3.3V, V DDCORE = 3.3V, TA = 25C) on the AT91EB55 Evaluation Board. They represent the power consumption on the VDDCORE power supply unless otherwise specified. Table 2. Power Consumption
Mode Conditions Fetch in ARM mode out of internal SRAM All peripheral clocks activated Normal Fetch in ARM mode out of internal SRAM All peripheral clocks deactivated All peripheral clocks activated Idle All peripheral clocks deactivated 1.78 4.59 mW/MHz 3.85 Consumption 6.55 Unit
Table 3. Power Consumption per Peripheral
Peripheral PIO Controller Timer/Counter Channel Timer/Counter Block (3 Channels) USART SPI ADC DAC PLL (1) (2) Notes: Consumption 0.22 0.15 0.42 0.40 0.40 0.23 0.29 2.6 mW mW/MHz Unit
1. Power consumption on the VDDPLL power supply. 2. With a reference frequency equal to 16 MHz, output frequency of 32 MHz and R = 287, C1 = 680 pF, C2 = 68 pF as loop filter.
Table 4. Battery Supply Voltage Consumption
Condition VDDBU = 3.0 V Power consumption on the VDDBU Power Supply. Without any capacitor connected to the RTC oscillator pins (XIN32, XOUT32) Consumption 0.9 Unit A
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Thermal and Reliability Considerations
Thermal Data In Table 5, the device lifetime is estimated with the MIL-217 standard in the "moderately controlled" environmental model (this model is described as corresponding to an installation in a permanent rack with adequate cooling air), depending on the device Junction Temperature. (For details see the section "Junction Temperature" on page 6.) Note that the user must be extremely cautious with this MTBF calculation: as the MIL217 model is pessimistic with respect to observed values due to the way the data/models are obtained (test under severe conditions). The life test results that have been measured are always better than the predicted ones. Table 5. MTBF Versus Junction Temperature
Junction Temperature (TJ) (C) 100 125 150 175 Estimated Lifetime (MTBF) (Year) 25 14 8 5
Table 6 summarizes the thermal resistance data related to the package of interest. Table 6. Thermal Resistance Data
Symbol JA JC Parameter Junction-to-ambient thermal resistance Junction-to-case thermal resistance PBGA176 20.1 Condition Still Air PBGA176 TQFP176 66 9.2 C/ W Package TQFP176 Typ 21 Unit
Reliability Data
The number of gates and the device die size are provided for the user to calculate reliability data with another standard and/or in another environmental model. Table 7. Reliability Data
Parameter Number of Logic Gates Number of Memory Gates Device Die Size Data 524 400 29.0 Unit K gates K gates mm2
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Junction Temperature
The average chip-junction temperature TJ in C can be obtained from the following: 1. 2. T J = T A + ( P D x JA )
T J = T A + ( P D x ( HEATSINK + JC ) )
Where: * * * * * JA = package thermal resistance, Junction-to-ambient (C/W), provided in Table 6 on page 5. JC = package thermal resistance, Junction-to-case thermal resistance (C/W), provided in Table 6 on page 5. HEAT SINK = cooling device thermal resistance (C/W), provided in the device datasheet. PD = device power consumption (W) estimated from data provided in the section "Power Consumption" on page 4. TA = ambient temperature (C).
From the first equation, the user can derive the estimated lifetime of the chip and thereby decide if a cooling device is necessary or not. If a cooling device is to be fitted on the chip, the second equation should be used to compute the resulting average chipjunction temperature TJ in C.
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Conditions
Timing Results The delays are given as typical values in the following conditions: * * * * * * * VDDIO = 5V VDDCORE = 3.3V Ambient Temperature = 25C Load Capacitance is 0 pF. The output level change detection is (0.5 x VDDIO). The input level is (0.3 x VDDIO) for a low-level detection and is (0.7 x VDDIO) for a high level detection. The Master Clock (MCK) source is a crystal oscillator connected to the XIN input.
The minimum and maximum values given in the AC characteristics tables of this datasheet take into account the process variation and the design. In order to obtain the timing for other conditions, the following equation should be used. t = T x ( ( VDDCORE x t DATASHEET ) + ( VDDIO x
( CSIGNAL x CSIGNAL ) ) )
where: * * * * * * T is the derating factor in temperature given in Figure 1. VDDCORE is the derating factor for the Core Power Supply given in Figure 2 on page 8. tDATASHEET is the minimum or maximum timing value given in this datasheet for a load capacitance of 0 pF. VDDIO is the derating factor for the IO Power Supply given in Figure 3 on page 9. CSIGNAL is the capacitance load on the considered output pin. (1) CSIGNAL is the load derating factor depending on the capacitance load on the related output pins given in Min and Max in this datasheet.
1. The user must take into account the package capacitance load contribution (CIN) described in Table 1 on page 3.
The input delays are given as typical values.
Note:
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Temperature Derating Factor
Figure 1. Derating Curve for Different Operating Temperatures
1.3
1.2
1.1
1
0.9
Typ Case Derating Factor is 1
0.8 -60 -40 -20 0 20 40 60 80 100 120 140 160 180 Operating Temperature (C)
Core Voltage Derating Factor
Figure 2. Derating Curve for Different Core Supply Voltages
3
2.5 Derating Factor Typ Case Derating Factor is 1
2
1.5
1
0.5 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8 Core Supply Voltage (V)
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IO Voltage Derating Factor
Figure 3. Derating Curve for Different IO Supply Voltages
1.55 1.50 1.45 1.40
Derating Factor
1.35 1.30 1.25 1.20 1.15 1.10 1.05 1.00 0.95
Typ Case Derating Factor is 1
3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 IO Supply Voltage (V)
Note:
The derating factor in this example is applicable only to timings related to output pins.
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Crystal Oscillator Characteristics
Table 8. RTC Oscillator Characteristics
Symbol 1/(tCPRTC) CL1, CL2 CL Parameter Crystal Oscillator Frequency Internal Load Capacitance (CL1 = CL2) Equivalent Load Capacitance Duty Cycle CL1 = CL2 = 12 pF Measured at the MCKO output pin Without any additional load capacitance and an ESR Max = 50 k With 13 pF external capacitor per pin and an ESR Max = 50 k 45 Conditions Min Typ 32.768 12 6 50 55 300 700 Max Unit KHz pF pF % ms ms
tST
Startup Time
Table 9. Main Oscillator Characteristics
Symbol 1/(tCPMAIN) CL1, CL2 CL Parameter Crystal Oscillator Frequency Internal Load Capacitance (CL1 = CL2) Equivalent Load Capacitance Duty Cycle With 10 pF external capacitor per pin and a 3 MHz crystal (1) With 10 pF external capacitor per pin and a 8 MHz crystal (2) With 10 pF external capacitor per pin and a 16 MHz crystal (3) With 10 pF external capacitor per pin and a 20 MHz crystal (3) Notes: 1. With ESR (Electrical Serie Resistor) maximum equal to 200 , CS maximum = 3 pF. 2. With ESR maximum equal to 100 , CS maximum = 7 pF. 3. With ESR maximum equal to 50 , CS maximum = 7 pF. CL1 = CL2 = 25 pF 45 Conditions Min 3 Typ 16 25 12.5 50 55 13 4.2 1.4 1 Max 20 Unit MHz pF pF % ms ms ms ms
tST
Startup Time
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Clock Waveforms
Table 10. Master Clock Waveform Parameters
Symbol 1/(tCPMCK) tCPMCK tCHMCK tCLMCK Parameter Master Clock Frequency Master Clock Period Master Clock High Half-period Master Clock Low Half-period 23.9 0.45 x tCPMCK 0.45 x tCPMCK 0.55 x tCPMCK 0.55 x tCPMCK Conditions Min Max 41.8 Units MHz ns ns ns
Table 11. Clock Propagation Times
Symbol tCDLH (1) tCDHL (1) Note: Parameter MCK Rising to MCKO Rising Edge Conditions CMCKO = 0 pF CMCKO derating MCK Falling to MCKO Falling Edge 1. Applicable only when MCKO outputs Master Clock. CMCKO = 0 pF CMCKO derating Min 7.5 0.053 7.7 0.059 Max 11.7 0.083 12.1 0.092 Units ns ns/pF ns ns/pF
Figure 4. Clock Waveform
tCLMCK
MCK
tCHMCK tCPMCK
0.5 VDDIO
MCKO
tCDLH tCDHL
0.5 VDDIO
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APMC Characteristics
Table 12. Master Clock Source Switch Times
MCK Source From RTC Oscillator Output PLL Output Main Oscillator Output PLL Output RTC Oscillator Output Main Oscillator Output PLL Output Freq. 1 To PLL Output RTC Oscillator Output PLL Output Main Oscillator Output Main Oscillator Output RTC Oscillator Output PLL Output Freq. 2 Min Switch Time Typ 4 x tCPRTC + 3 x tCPPLL 5 x tCPRTC 5 x tCPRTC + 3 x tCPPLL 4 x tCPRTC + 3 x tCPMAIN 3 x tCPRTC + 3 x tCPMAIN 5 x tCPRTC 7 x tCPRTC + 3 x tCPPLL2 Max
Backup Battery Reset Signal
Internally to the device, the NRSTBU signal is maintained low for RSTBU1 time after the rising edge of the external signal. Therefore, the NRSTBU signal needs to be asserted only during the VDDBU power ramp up by the user. This feature covers the requirement of an NRSTBU signal assertion of 10(tCPRTC) at a minimum at VDDBU power up.
Table 13. Backup Battery Reset Signal Internal Assertion Delay
Symbol RSTBU1 Parameter NRSTBU Internal Assertion Delay Typical Internal Delay 1 Units s
Figure 5. NRSTBU Assertion Sequence
VDDBU 0V VDDBU
RTC Oscillator Output
MCKO
(1)
External Signal NRSTBU Internal Signal
Note: 1. The MCKO Signal is certified to be valid at the NRSTBU Internal Signal rising edge.
RSTBU1
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Wake Up Signal Table 14. Wake Up Minimum Pulse Width
Symbol WK1 Parameter Wake Up Minimum Pulse Width Min Pulse Width 46 Units s
Figure 6. Wake Up Signal
Wake Up
WK1
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Analog Characteristics
ADC
Table 15. Channel Conversion Time Relative to ADC Clock
Parameter Channel Conversion Time ADC Clock Frequency Min Typ 11 800 Max Units cycle kHz
Table 16. External Voltage Reference Input
Symbol VREF Parameter ADVREF Input Voltage Range ADVREF Input Resistance Min 2.4 12 Max VDDA 24 Units V k
Table 17. Analog Inputs
Parameter Input Voltage Range Input Leakage Current Input Capacitance Min 0 -0.1 Typ Max VREF 0.1 30 Units V A pF
Table 18. Dynamic Performance
Parameter Signal-to-noise Ratio Total Harmonic Distortion Inter-modulation Distortion Channel-to-Channel Isolation Conditions Min Max Units dB dB dB dB
Table 19. Transfer Characteristics
Parameter Resolution Integral Non-linearity VDDA = 3.3V 10%, ADVREF = VDDA ADC Clock = 500 kHz ADC Clock = 800 kHz Conditions Min Max 10 3 LSB 4 Units Bit
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Table 19. Transfer Characteristics
Parameter Differential Non-linearity Offset Error Gain Error Conditions VDDA = 3.3V 10%, ADVREF = VDDA ADC Clock = 500 kHz ADC Clock = 800 kHz Min Max 2 LSB 4 2 4 LSB LSB Units
DAC
Table 20. DAC Timing Characteristics
Parameter Channel Setting Time Conditions 0.85V to 1.85V or 1.85V to 0.85V Min Max 6 Units s
Table 21. External Voltage Reference Input
Symbol VREF Parameter DAVREF Input Voltage Range DAVREF Input Resistance Min 2.4 12 Max VDDA 24 Units V k
Table 22. Output Op Amp Characteristics
Parameter Output Voltage Range Input Offset Voltage Output Source Current Output Sink Current Slew Rate Startup Time Overshoot Rise or Fall Load = 50 pF /10 k (in parallel) 100 mV@ vcm 0.2 100 20 Conditions Min 0 Max VREF 10 5 5 Units V mV mA mA V/s s %
Table 23. Dynamic Performance
Parameter Total Harmonic Distortion Conditions Min Max TBD Units dB
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Table 24. Transfer Characteristics
Parameter Resolution Integral Non-linearity Differential Non-linearity Offset Error Gain Error VDDA = 3.3V 10%, DAVREF > 2.4V VDDA = 3.3V 10%, DAVREF > 2.4V Conditions Min Max 10 4 4 2 4 Units Bit LSB LSB LSB LSB
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AC Characteristics
EBI Signals Relative to MCK
The following tables show timings relative to operating condition limits defined in the section "Timing Results" on page 7 Table 25. General-purpose EBI Signals
Symbol EBI1 Parameter MCK Falling to NUB Valid Conditions CNUB = 0 pF CNUB derating MCK Falling to NLB/A0 Valid CNLB = 0 pF CNLB derating MCK Falling to A1 - A23 Valid CADD = 0 pF CADD derating MCK Falling to Chip Select Change NWAIT Setup before MCK Rising NWAIT Hold after MCK Rising CNCS = 0 pF CNCS derating Min 8.9 0.053 8.3 0.053 8 0.053 8.2 0.053 -0.4 5.9 Max 17 0.092 14.8 0.092 15.2 0.092 15.6 0.092 Units ns ns/pF ns ns/pF ns ns/pF ns ns/pF ns ns
EBI2
EBI3
EBI4 EBI5 EBI6
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. Table 26. EBI Write Signals
Symbol EBI7 Parameter MCK Rising to NWR Active (No Wait States) MCK Rising to NWR Active (Wait States) MCK Falling to NWR Inactive (No Wait States) MCK Rising to NWR Inactive (Wait States) MCK Rising to D0 - D15 Out Valid Conditions CNWR = 0 pF CNWR derating CNWR = 0 pF CNWR derating CNWR = 0 pF CNWR derating CNWR = 0 pF CNWR derating CDATA = 0 pF CDATA derating NWR High to NUB Change CNUB = 0 pF CNUB derating NWR High to NLB/A0 Change CNLB = 0 pF CNLB derating NWR High to A1 - A23 Change CADD = 0 pF CADD = derating NWR High to Chip Select Inactive CNCS = 0 pF CNCS derating C = 0 pF EBI16 Data Out Valid before NWR High (No Wait States) (1) CDATA derating CNWR derating C = 0 pF EBI17 Data Out Valid before NWR High (Wait States) (1) Data Out Valid after NWR High NWR Minimum Pulse Width (No Wait States) (1) NWR Minimum Pulse Width (Wait States) (1) CNWR = 0 pF CNWR derating CNWR = 0 pF CNWR derating CDATA derating CNWR derating EBI18 EBI19 EBI20 Notes: Min 8.2 0.059 9 0.059 8.6 0.053 8.9 0.053 8.3 0 4.8 0.053 4.6 0.059 4.4 0.059 4.4 0.053 tCHMCK - 1.9 - 0.086 0.083 n x tCPMCK - 1.5 (2) -0.086 0.083 4.4 tCHMCK + 0.3 -0.009 n x tCPMCK - 0.2 -0.009
(2)
Max 13 0.092 14.1 0.092 13.5 0.083 13.9 0.083 15.4 0.086 9.6 0.092 7.4 0.092 8.1 0.092 8.6 0.083
Units ns ns/pF ns ns/pF ns ns/pF ns ns/pF ns ns/pF ns ns/pF ns ns/pF ns ns/pF ns ns/pF ns ns/pF ns/pF ns ns/pF ns/pF ns ns ns/pF ns ns/pF
EBI8
EBI9
EBI10
EBI11
EBI12
EBI13
EBI14 EBI15
1. The derating factor is not to be applied to tCHMCK or tCPMCK. 2. n = number of standard wait states inserted.
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Table 27. EBI Read Signals
Symbol EBI21 Parameter MCK Falling to NRD Active (1) Conditions CNRD = 0 pF CNRD derating MCK Rising to NRD Active (2) CNRD = 0 pF CNRD derating MCK Falling to NRD Inactive (1) CNRD = 0 pF CNRD derating MCK Falling to NRD Inactive (2) D0-D15 in Setup before MCK Falling D0-D15 in Hold after MCK Falling (5) NRD High to NUB Change CNUB = 0 pF CNUB derating NRD High to NLB/A0 Change CNLB = 0 pF CNLB derating NRD High to A1-A23 Change CADD = 0 pF CADD derating NRD High to Chip Select Inactive CNCS = 0 pF CNCS derating Data Setup before NRD High (5) CNRD = 0 pF CNRD derating Data Hold after NRD High (5) CNRD = 0 pF CNRD derating NRD Minimum Pulse Width (1) (3) CNRD = 0 pF CNRD derating CNRD = 0 pF EBI34 Notes: 1. 2. 3. 4. 5. NRD Minimum Pulse Width
(2) (3) (5)
Min 8.5 0.059 7.7 0.059 8.3 0.053 7.9 0.053 -2.2 6.8 5 0.053 4.7 0.059 4.5 0.059 4.4 0.053 11 0.083 -3.6 -0.053 (n +1) x tCPMCK - 1.5 (4) -0.009 n x tCPMCK + (tCHMCK - 1.7)(4) -0.009
Max 14.5 0.092 14.2 0.092 14.5 0.083 12.4 0.083
Units ns ns/pF ns ns/pF ns ns/pF ns ns/pF ns ns
EBI22
EBI23
EBI24 EBI25 EBI26 EBI27
CNRD = 0 pF CNRD derating
9.6 0.092 7.4 0.092 8 0.092 8.5 0.083
ns ns/pF ns ns/pF ns ns/pF ns ns/pF ns ns/pF ns ns/pF ns ns/pF ns ns/pF
EBI28
EBI29
EBI30
EBI31
EBI32
EBI33
CNRD derating Early Read Protocol. Standard Read Protocol. The derating factor is not to be applied to tCHMCK or tCPMCK. n =number of standard Wait States inserted. Only one of these two timings needs to be met.
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Table 28. EBI Read and Write Control Signals. Capacitance Limitation
Symbol TCPLNRD(1) TCPLNWR(2) Notes: Parameter Master Clock Low Due to NRD Capacitance Conditions CNRD = 0 pF CNRD derating Master CLock Low Due to NWR Capacitance CNWR = 0 pF CNWR derating Min 11.2 0.083 10.3 0.083 Max Units ns ns/pF ns ns/pF
1. If this condition is not met, the action depends on the read protocol intended for use. * Early Read Protocol: Programing an additional tDF (Data Float Output Time) cycle. * Standard Read Protocol: Programming an additional tDF Cycle and an additional wait state. 2. Applicable only for chip select programmed with 0 wait state. If this condition is not met, at least one wait state must be programmed.
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Figure 7. EBI Signals Relative to MCK
MCK EBI4 EBI4
NCS EBI3 A1 - A23 EBI5 NWAIT EBI6
EBI1/EBI2 NUB/NLB/A0 EBI21 EBI33 NRD(1) EBI22 NRD(2) EBI31
EBI23
EBI27-30
EBI24 EBI34 EBI32 EBI25 EBI26
D0 - D15 Read EBI7 NWR (No Wait States) EBI8 EBI20 NWR (Wait States) EBI17 EBI11 D0 - D15 to Write No Wait Wait EBI16 EBI18 EBI18 EBI10 EBI9 EBI19 EBI12-15
Notes:
1. Early Read Protocol. 2. Standard Read Protocol.
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Peripheral Signals
USART Signals The inputs must meet the minimum pulse width and period constraints shown in Table 29 and Table 30, and represented in Figure 8.
Table 29. USART Input Minimum Pulse Width
Symbol US1 Parameter SCK/RXD Minimum Pulse Width Min Pulse Width 5(tCPMCK/2) Units ns
Table 30. USART Minimum Input Period
Symbol US2 Parameter SCK Minimum Input Period Min Input Period 9(tCPMCK/2) Units ns
Figure 8. USART Signals
US1
RXD US2 US1 SCK
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SPI Signals The inputs must meet the minimum pulse width and period constraints shown in Table 31 and Table 32 and as represented in Figure 9. Table 31. SPI Input Minimum Pulse Width
Symbol SPI1 Parameter SPK/MISO/MOSI/NSS Minimum Pulse Width Min Pulse Width 3(tCPMCK/2) Units ns
Table 32. SPI Minimum Input Period
Symbol SPI2 Parameter SPCK Minimum Input Period Min Input Period 5(tCPMCK/2) Units ns
Figure 9. SPI Signals
SPI1
SPCK/MISO/ MOSI/NSS SPI2 SPI1 SPCK
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Timer/Counter Signals
Due to internal synchronization of input signals, there is a delay between an input event and a corresponding output event. This delay is 3(tCPMCK) in Waveform Event Detection mode and 4(tCPMCK) in Waveform Total-count Detection mode. The inputs must meet the minimum pulse width and minimum input period shown in Table 33 and Table 34, and as represented in Figure 10.
Table 33. Timer Input Minimum Pulse Width
Symbol TC1 Parameter TCLK/TIOA/TIOB Minimum Pulse Width Min Pulse Width 3(tCPMCK/2) Units ns
Table 34. Timer Input Minimum Period
Symbol TC2 Parameter TCLK/TIOA/TIOB Minimum Input Period Min Input Period 5(tCPMCK/2) Units ns
Figure 10. Timer Input
3(tCPMCK/2) MCK TC1 TIOA/ TIOB/ TCLK TC2 3(tCPMCK/2)
Reset Signals
A minimum pulse width is necessary, as shown in Table 35 and as represented in Figure 11.
Table 35. Reset Minimum Pulse Width
Symbol RST1 Parameter NRST Minimum Pulse Width Min Pulse Width 310 Units s
Figure 11. Reset Signal
RST1 NRST
Only the NRST rising edge is synchronized with MCK. The falling edge is asynchronous.
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Advanced Interrupt Controller Signals Inputs must meet the minimum pulse width and minimum input period shown in Table 36 and Table 37, and represented in Figure 12.
Table 36. AIC Input Minimum Pulse Width
Symbol AIC1 Parameter FIQ/IRQ[6:0] Minimum Pulse Width Min Pulse Width 3(tCPMCK/2) Units ns
Table 37. AIC Input Minimum Period
Symbol AIC2 Parameter AIC Minimum Input Period Min Input Period 5(tCPMCK/2) Units ns
Figure 12. AIC Signals
AIC2 MCK AIC1 FIQ/IRQ [6:0]Input
Parallel I/O Signals
The inputs must meet the minimum pulse width shown in Table 38 and represented in Figure 13.
Table 38. PIO Input Minimum Pulse Width
Symbol PIO1 Parameter PIO Input Minimum Pulse Width Min Pulse Width 3(tCPMCK/2) Units ns
Figure 13. PIO Signal
PIO1 PIO Inputs
25
1727E-ATARM-01/04
ICE Interface Signals Table 39. ICE Interface Timing Specifications
Symbo l ICE0 ICE1 ICE2 ICE3 ICE4 ICE5 ICE6 ICE7 ICE8 Parameter NTRST Minimum Pulse Width NTRST High Recovery to TCK High NTRST High Removal from TCK High TCK Low Half-period TCK High Half-period TCK Period TDI, TMS, Setup before TCK High TDI, TMS, Hold after TCK High TDO Hold Time CTDO = 0 pF CTDO derating TCK Low to TDO Valid CTDO = 0 pF CTDO derating Conditions Min 19.3 0.4 0.5 42.3 40.3 82.5 0.9 0.7 6.4 0 14 0.092 Max Units ns ns ns ns ns ns ns ns ns ns/pF ns ns/pF
ICE9
Figure 14. ICE Interface Signal
NTRST ICE0
ICE1 TCK ICE5
ICE2
ICE3
ICE4
TMS/TDI ICE6 ICE7
TDO ICE8 ICE9
26
AT91M55800A
1727E-ATARM-01/04
AT91M55800A
JTAG Interface Signals Table 40. JTAG Interface Timing Specifications
Symbo l JTAG0 JTAG1 JTAG2 JTAG3 JTAG4 JTAG5 JTAG6 JTAG7 JTAG8 Parameter NTRST Minimum Pulse Width NTRST High Recovery to TCK Toggle NTRST High Removal from TCK Toggle TCK Low Half-period TCK High Half-period TCK Period TDI, TMS Setup before TCK High TDI, TMS Hold after TCK High CTDO = 0 pF TDO Hold Time CTDO derating CTDO = 0 pF JTAG9 JTAG10 JTAG11 JTAG12 TCK Low to TDO Valid CTDO derating -0.4 3.4 COUT = 0 pF Device Outputs Hold Time COUT derating COUT = 0 pF JTAG13 TCK to Device Outputs Valid COUT derating 5.3 0 12.6 0.086 Conditions Min 19.3 -0.1 2.7 10.9 3 13.8 1.5 1.9 3.8 0 8.5 0.086 Max Units ns ns ns ns ns ns ns ns ns ns/pF ns ns/pF ns ns ns ns/pF ns ns/pF
Device Inputs Setup Time Device Inputs Hold Time
27
1727E-ATARM-01/04
Figure 15. JTAG Interface Signal
JTAG0 NTRST JTAG1 JTAG5 TCK JTAG3 JTAG4 JTAG2
TMS/TDI JTAG6 JTAG7
TDO JTAG8 JTAG9 Device Inputs JTAG10 JTAG11
Device Outputs JTAG12 JTAG13
28
AT91M55800A
1727E-ATARM-01/04
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